Public Abstract

DE-SC0025379: Neuron blocks using HfZrO/GaN field effect transistors for energy efficiency computing

Award Status: Active

Institution: University Of Delaware, Newark, DE
UEI: T72NHKM259N3
DUNS: 059007500

Most Recent Award Date: 09/11/2024
Number of Support Periods: 1
PM: Pino, Robinson

Current Budget Period: 09/01/2024 - 08/31/2025
Current Project Period: 09/01/2024 - 08/31/2026
PI: Zeng, Yuping

Supplement Budget Period: N/A

Public Abstract

Neuron blocks using HfZrO/GaN field effect transistors for energy efficiency computing PI: Yuping Zeng, Assistant Professor, Department of Electrical and Computer Engineering, University of Delaware Newark, DE, 19716 Conventional von Neumann architecture consists of chips that are designed with a clock that continuously reads a sequential instruction set. In contrast, neuromorphic computing emulates human brain without using a clock and creates a huge parallel sea of neurons, each one of which operates without any prescribed order, providing a new paradigm to establish artificial intelligence in terms of energy efficiency, computing in memory and dynamic learning. To strengthen the neuromorphic computing community, a broad range of scientific discipline from material science to devices, to computer science, to neuroscience, etc., has to be involved to help to solve the grand challenges. For instance, how can we build or integrate the necessary computing hardware to realize energy efficiency? To answer this question, implementing novel functional circuits with new energy efficiency devices is critically needed. From the functional point of view, neurons can all be described as circuits that have one or more synapse blocks, responsible for receiving spikes from other neurons, integrating them over time and converting them into currents, as well as a soma block, responsible for the spatio-temporal integration of the input signals and generation of the output analog action potentials and digital spike events. Silicon neurons (SiNs) are hybrid analog/digital very large-scale integration circuits that emulate the electrophysiological behavior of real neurons and conductances. Hardware emulations of neural systems that use SiNs operate in real-time, and the speed of the network is independent of the number of neurons or their coupling. SiNs offer a medium in which neuronal networks can be emulated directly in hardware rather than simply simulated on a general-purpose computer. They are much more energy efficient than simulations executed on general purpose computers, so they are suitable for real-time large-scale neural emulations. However, these SiNs are circuits that are built from conventional silicon metal oxide semiconductor field effect transistors, which cannot operate fast and they consume much power. In contrast, GaN field effect transistors have received attention for such applications because of their advantages in speed and power, with which we can build energy efficiency neuron circuits. Here, PI proposes to develop neuron blocks (three circuits: log-domain circuit, subthreshold first-order low pass filter circuit, non-linear current-mode low pass filter circuit) by leveraging PI’s group newly developed HfZrO/GaN field effect transistors. The developed technology has shown record high performance (highlighted by more than 10 news media) in terms of speed and power. With annealed HfZrO film, the device showed (1) much lower off-current and subthreshold slope, which are beneficial for the power consumption; (2) high on-off ratio, which is beneficial for the operation speed. Such a new generation semiconductor technology offers high electron mobility and wide bandgap, enabling its benefits in terms of size, weight, and power efficiency of the circuits and systems. Our aims are: (1) developing the device model in advanced design system; (2) using the developed model to simulate the three circuits in advanced design system; (3) implementing and measuring the three circuits using our Nanofab facility. We will implement the circuits using both depletion mode transistors and enhancement mode transistors for threshold voltage adjustment and perform the circuit testing. We expect to develop these building blocks for conductance-based synapses; robust emulation of emergent iono-neuronal dynamics, reproducing also chaotic bursting as observed in pacemaker cells;Low-pass filter functionality with tunable dynamic conductances. It is expected that using our developed field effect transistors (HfZrO/GaN transistors), we will be able to achieve energy efficient neuron building blocks (the above-mentioned three circuits). The developed new circuits are beneficial for energy efficient neuromorphic computing system.

Neuron blocks using HfZrO/GaN field effect transistors for energy efficiency computing

PI: Yuping Zeng, Assistant Professor,

Department of Electrical and Computer Engineering,

University of Delaware

Newark, DE, 19716

Conventional von Neumann architecture consists of chips that are designed with a clock that continuously reads a sequential instruction set. In contrast, neuromorphic computing emulates human brain without using a clock and creates a huge parallel sea of neurons, each one of which operates without any prescribed order, providing a new paradigm to establish artificial intelligence in terms of energy efficiency, computing in memory and dynamic learning.

To strengthen the neuromorphic computing community, a broad range of scientific discipline from material science to devices, to computer science, to neuroscience, etc., has to be involved to help to solve the grand challenges. For instance, how can we build or integrate the necessary computing hardware to realize energy efficiency? To answer this question, implementing novel functional circuits with new energy efficiency devices is critically needed.

From the functional point of view, neurons can all be described as circuits that have one or more synapse blocks, responsible for receiving spikes from other neurons, integrating them over time and converting them into currents, as well as a soma block, responsible for the spatio-temporal integration of the input signals and generation of the output analog action potentials and digital spike events.

Silicon neurons (SiNs) are hybrid analog/digital very large-scale integration circuits that emulate the electrophysiological behavior of real neurons and conductances. Hardware emulations of neural systems that use SiNs operate in real-time, and the speed of the network is independent of the number of neurons or their coupling. SiNs offer a medium in which neuronal networks can be emulated directly in hardware rather than simply simulated on a general-purpose computer. They are much more energy efficient than simulations executed on general purpose computers, so they are suitable for real-time large-scale neural emulations. However, these SiNs are circuits that are built from conventional silicon metal oxide semiconductor field effect transistors, which cannot operate fast and they consume much power. In contrast, GaN field effect transistors have received attention for such applications because of their advantages in speed and power, with which we can build energy efficiency neuron circuits.

Here, PI proposes to develop neuron blocks (three circuits: log-domain circuit, subthreshold first-order low pass filter circuit, non-linear current-mode low pass filter circuit) by leveraging PI’s group newly developed HfZrO/GaN field effect transistors. The developed technology has shown record high performance (highlighted by more than 10 news media) in terms of speed and power. With annealed HfZrO film, the device showed (1) much lower off-current and subthreshold slope, which are beneficial for the power consumption; (2) high on-off ratio, which is beneficial for the operation speed. Such a new generation semiconductor technology offers high electron mobility and wide bandgap, enabling its benefits in terms of size, weight, and power efficiency of the circuits and systems.

Our aims are: (1) developing the device model in advanced design system; (2) using the developed model to simulate the three circuits in advanced design system; (3) implementing and measuring the three circuits using our Nanofab facility. We will implement the circuits using both depletion mode transistors and enhancement mode transistors for threshold voltage adjustment and perform the circuit testing.

We expect to develop these building blocks for conductance-based synapses; robust emulation of emergent iono-neuronal dynamics, reproducing also chaotic bursting as observed in pacemaker cells;Low-pass filter functionality with tunable dynamic conductances. It is expected that using our developed field effect transistors (HfZrO/GaN transistors), we will be able to achieve energy efficient neuron building blocks (the above-mentioned three circuits). The developed new circuits are beneficial for energy efficient neuromorphic computing system.